Advanced CMOS and BiCMOS technologies employ twin (n and p) wells in order to allow simultaneous optimization of the NMOS and PMOS transistors. The conventional twin well formation processes employ one or two microlithography masking steps. The two-mask fabrication process has the advantage that it does not degrade the silicon surface planarity or topography. This is an important requirement in advanced sub-0.5 .mu.m CMOS and BiCMOS technologies where even a small (e.g. a few thousand .ANG.) step between the n-well and p-well regions can result in gate length variations between the NMOS and PMOS transistors (due to the limited depth-of-focus orDOF budget in advanced photo-lithography tools). The CMOS transistor gate length variations (after patterning and etch) can degrade manufacturability and yield. As a result, the process simplicity of the conventional one-mask fabrication process is not a strong and sufficient advantage/improvement to justify its use in sub-0.5 .mu.m semiconductor technologies since the one-mask process consumes silicon when masking a particular area to provide a well region. Such oxidation-induced silicon consumption results in uneven planarity of the PMOS and NMOS gates as shall be explained below. The smaller the device gate-lengths the more critical uneven planarity becomes. As discussed, the potential gate length variability caused by the nonplanar n and p well surfaces and DOF limitation imposes the above-mentioned obstacle. The surface topography problem in the conventional one-mask fabrication process is generated by a selective thermal oxidation process. An oxide/nitride stack is patterned and is used (usually along with the photoresist mask) as an ion implantation mask to define one of the wells. After removal of the photoresist, an oxidation step is performed which selectively defines an oxide hard mask over the implanted region. A second ion implantation step is used to define the second (opposite) well regions. As this process flow indicates, a surface topography or step is produced between the n and p well regions due to the silicon consumption by the selective thermal oxidation step.
Thus, advanced sub-0.5 .mu.m CMOS and BiCMOS technologies usually rely on a two-mask (non-self aligned) process to define the n-well and p-well regions. In the two-mask process, patterned photoresist (or hard mask) layers are used as ion implantation masks. No surface step or topography is produced, therefore allowing uniform PMOS and NMOS gate patterning. However, the use of one additional masking process adds to the overall process cost and complexity.
Therefore, there is a need for a simple self-aligned manufacturable single-mask process for formation of n-well and p-well regions without the surface topography and gate patterning DOF problems of the conventional one-mask methods.